The inventive concepts relate to semiconductor devices having device isolation structures, and more specifically to semiconductor devices having device isolation structures that can suppress the degradation of transistor characteristics and methods of forming the same.
In highly integrated semiconductor devices, device isolation layers are formed on a semiconductor substrate to electrically isolate semiconductor devices. The device isolation layer may be formed by forming a trench and filling the trench with a dielectric material. In the meantime, ahead of filling the trench with the dielectric material, a liner of silicon nitride can be formed on the inner wall of the trench to relieve stress generated at the inner wall of the trench. A MOS transistor may be formed on the semiconductor substrate on which the device isolation layer is formed.
When there is a great difference between voltages at a gate electrode and a drain region during the operation of a MOS transistor, hot electrons may be generated in the channel region adjacent the drain region. The hot electrons may be trapped to a silicon nitride pattern located at the boundary between the channel region and the device isolation layer. Due to the hot electrons trapped to the silicon nitride pattern, holes may be induced at the boundary between the channel region and the device isolation layer.
Meanwhile, in the case of a PMOS transistor where majority carriers are holes, the holes induced at the boundary between the channel region and the device isolation layer may extend the drain region. As a result, the channel length of the PMOS transistor may be decreased to cause a punch-through phenomenon. Accordingly, leakage current may be generated at the transistor in an OFF-state to degrade characteristics of the transistor.